In modem digital receivers, the digital complex baseband signal recovered from the analog-to-digital converter invariably contains residual carrier frequency errors due to mismatches between the transmit and receive local oscillators. These residual carrier errors must be removed before the baseband signal can be further processed and outputted. One system for correcting this residual carrier error uses a carrier recovery loop circuit that provides compensating feedback phase and frequency offsets to the corrupted complex baseband signal. FIG. 1 illustrates the interconnectivity of such a carrier recovery loop 20 between an equalizer 22 and an air interface processor 24, and a carrier recovery (CR) subsystem 25.
As further shown in FIG. 2, a typical CR loop 20 consists of the following components: a phase derotator 26, a slicer 27, and the CR subsystem 25 consisting of a phase error detector 28, a loop filter 30, a carrier acquisition control 32, a phase accumulator and sine and cosine look-up table (LUT) 34, and a CR lock detector 36. In operation, the CR loop 20 remains inactive following power-up until the air interface processor (AIP) 24 in FIG. 1 gives a carrier-synchronization-enable signal. The carrier loop 20 works in collaboration with the equalizer 22. The AIP 24 activates the CR loop 20 once the equalizer Constant Modulus Algorithm (CMA) mode has converged sufficiently. It is assumed that the frequency offset encountered by the CR loop 20 is in the order of ±5% of the highest symbol rate of the digital demodulator. The carrier loop 20 can operate at a rate of one sample per symbol or at a reduced rate as programmed by the air interface processor 24. In lower data rate applications where the equalizer 22 is not required, the equalizer taps are by passed. However, the slicer 27 will still continue to feed the quantized decisions (qn) to CR loop 20. Typically, the input (yn) to the slicer 27 has a word length of 12-bits and the output (qn) is 3-bits wide. Both yn and qn feed the CR sub-system 25.
When the initial frequency offset encountered by the carrier recovery loop 20 is in the order of ±5% of the symbol rate, the CR loop 20 cannot always lock on to, and compensate for, the incoming offset frequency in an unaided fashion. Therefore, the following acquisition technique has been used in prior art sytems to achieve better carrier lock. The frequency of the VCO is swept linearly across the range spanning the maximum frequency offset encountered by the receiver. This is done by feeding a linearly changing dc-voltage to the output of the loop filter of FIG. 2 prior to the phase accumulator 34. When the VCO frequency and the residual offset frequency at the phase derotator 26 input coincide, the carrier loop 20 will lock, and the lock detector 36 indicates to the acquisition control unit 32 to freeze the dc sweep value. The CR loop 20 enters tracking mode at this point. FIG. 3 illustrates the carrier acquisition process of a typical carrier recovery loop sub-system.
In a high-speed receiver system, hardware realization of the multipliers and adders used in the CR sub-system 25 can produce pipeline delays that are based on the number of hardware clock cycles available for performing computations. Given a maximum operating clock frequency of the system, there are a limited number of hardware clock cycles between consecutive data samples at the higher data rates. For instance, at data rates of 155 Mbits per second, the maximum clock frequency becomes close or equal to the typical data sampling-rate. Each hardware multiplication and addition operation in the carrier recovery feedback loop 20 will therefore introduce pipeline delays. The presence of such delays in the feedback loop 20 introduces instabilities in the carrier acquisition scheme due to the addition of unwanted poles in the closed loop system response. When there is an excessive number of delays present in the feedback loop, the carrier loop 20 is not able to achieve carrier lock even with an aided acquisition scheme.
It is, therefore, desirable to provide a method and system for alleviating the adverse effects of pipeline delays in a carrier recovery loop.